Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is then sliced into individual wafers. In some applications, a multi-layered structure (sometimes generically referred to as a multi-layered structure or simply as a wafer) may be used. A common form of multi-layered structure is a semiconductor on insulator structure, one of the most common of which is a silicon-on-insulator (SOI) wafer. An SOI wafer typically includes a thin layer of silicon atop a dielectric layer (i.e., an insulating layer) which is in turn disposed on a substrate (i.e., a handle wafer). Typically the substrate or handle wafer is silicon.
In some approaches, a process for making a semiconductor on insulator wafer may include implanting particles (e.g., hydrogen atoms or a combination of hydrogen and helium atoms) at a specified depth beneath the front surface of a donor wafer. The implanted particles form a damage layer which may be or become a cleave plane in the donor wafer at the specified depth at or near the depth at which they were implanted. The surface of the donor wafer may be cleaned to remove material deposited on the wafer during the implantation process. The donor may then be bonded to a handle wafer and the bonded structure. In some approaches the donor wafer and/or the handle wafer may have a dielectric layer deposited on the surface prior to or after the implantation, but prior to bonding. The donor and handle may then be bonded such that the dielectric layer becomes sandwiched between the donor and the handle. The donor may thereafter be cleaved to form a semiconductor-on-insulator structure. If no dielectric later is present, the structure formed would be a semiconductor-on-substrate, such as silicon germanium on silicon or even silicon on silicon. In instances where the donor is a silicon wafer and the dielectric layer is an insulator such as silicon dioxide, the structure formed would be an SOI wafer.
Typically, the assembly of such structures may include an annealing process performed in environments (such as nitrogen or oxygen) that do not significantly improve the surface morphology. For example, oxidation and/or nitridation of a silicon surface prevents the surface from getting smoother during the annealing process. Moreover, since the surface during the anneal is damaged, a low oxidation rate must be used to avoid creating secondary defects in the SOI layer. One consequence of the low oxidation rate is that the damage layer existing at the top surface of the SOI film is not removed during the anneal. During a final thermal step used to smooth and thin the SOI to a target thickness, the residual damage can be preferentially etched so as to form small features on the completed surface. The surface features can scatter light during an inspection with a standard laser based surface inspection tool resulting in a high background noise level.
As a result, current manufacturing processes can result in haze-related patterns when inspecting the final product. One type of haze-related pattern is the “hour-glass” pattern, which can result from surface roughness (e.g., see FIG. 2). Another source of noise results from the interaction of the final smoothing process with very small, benign, bulk inhomogeneities in the SOI film, which form very shallow but detectable features during automated surface inspection using laser scattering methods. These types of haze-related patterns typically occur in a ring or central light point defect patterns such as is seen in FIG. 3.
These haze-related patterns lead to decreased performance of the final wafer product via implant damage, surface roughness and light point defects (LPDs). There remains an unfulfilled need, therefore, for processing SOI structures to reduce any resulting LPD defects and to reduce any surface roughness in order to avoid haze-related patterns.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.